1. Field Of the Invention
This invention relates to integrated circuit fabrication and more particularly to integrated circuit processing parameters and step sequences which demonstrates substantially uniform removal of a silicon dioxide layer overlying single crystal silicon or polycrystalline silicon.
2. Description of the Relevant Art
The process of forming an oxide (SiO.sub.2) upon a silicon-based material is often termed oxidation. While there are numerous ways in which to form an oxide, thermal oxide growth or "thermal oxidation" remains the most viable. Thermal oxidation involves subjecting the silicon-based material to an oxygen ambient, either dry oxygen or moist oxygen (H.sub.2 O-based oxygen). As the oxide grows, it consumes a portion of the silicon-based material, wherein the silicon-based material is either single crystal silicon or polycrystalline silicon.
Thermal oxide serves numerous purposes, two of which are to passivate the silicon-based surface and mask against ion implantation and diffusion therethrough. Openings within thermal oxide allow passage of dopants. Conversely, areas having thermal oxide substantially prevent (mask) dopant passage. The presence of thermal oxide prevents (passivates against) formation of certain types of thin films upon the oxide while allowing those types of films to form in areas void of oxide.
Exemplary applications of a thermal oxide include, for example, oxide formed on a sidewall of polysilicon to mask against placement of heavy dopants in the perimeter of the channel region. Thermally grown sidewall spacers are used predominantly in the well-known lightly doped drain (LDD) process. Removal of oxide in the source and drain while retaining the sidewall spacer not only allows placement of heavy dopants spaced from the channel within the underlying silicon substrate, but also allows subsequent formation of silicide in those areas void of oxide. Presence of sufficiently thick oxide elsewhere on the topographical substrate masks against silicide formation by preventing interaction of the refractory metal to the underlying silicon.
Proper placement of a sidewall spacer in the LDD process helps minimize short channel effects and hot carrier injection problems. Moreover, accurate and uniform removal of oxide adjacent the sidewall spacer, from the source and drain regions, allows high conductivity silicide growth in the metallization contact areas. If excessive oxide is allowed to remain in the contact areas, that oxide would prevent sufficient silicide formation in the localized areas. Further, the presence of unacceptable thickened areas of oxide could negatively trap charge at the contact. The trapped charge could deleteriously effect the resulting contact conductivity. Trapped charge often results from mobile ions introduced into the oxide as it is grown. The mobile ions arise from, for example, the thermal furnace, oxidizing ambient, wafer handling equipment, etc. Further, defects within the oxide, such as broken bonds, can further introduce traps within the oxide. Traps resulting from impurities or bond irregularities in the oxide are part and parcel of normal oxide growth, however, these deficiencies will be removed if the oxide is adequately and uniformly removed across the entire contact area.
Non-uniform removal of oxide in contact areas can therefore result in localized regions of thickened oxide existing across the contact area. Those localized regions can lead to a "thinning" of silicide and the charge trapping problems associated therewith.
An early technique used to remove oxide from source and drain contact regions involves wet etch removal. The liquid etchant used for wet etching of oxide demonstrates high selectivity to both substrate and the masking layer (i.e., high etch rate to oxide as opposed to the underlying silicon-based material and the overlying photoresist). Wet etching, however, is typically isotropic allowing significant undercutting into the gate oxides and field oxides adjacent the source and drain contact areas. Since many devices are formed with less than, for example, 2.0 .mu.m critical dimension, oxide film less than 1.0 .mu.m in thickness cannot be removed while retaining those critical dimensions. An alternative pattern transfer process is therefore needed. The alternative pattern transfer process must be significantly anisotropic, using a dry etch or plasma etch technique.
Dry etching is capable of reproducing a feature of a mask upon a device topography with high fidelity. That is, the anisotropic dry etch process allows pattern transfer of critical dimensions of less than, for example, 1.0 .mu.m. While dry etching is more attuned to modern VLSI device fabrication, to be a fully useful process, dry etching must be highly selective against etching the silicon-based material under the oxide being etched. The dry etching process must also be uniformly applied across each contact area as well as across the entire wafer. Still further, dry etching must cause minimum damage to the underlying silicon-based material.
To enhance dry etch selectivity and uniformity, many researchers have experimented with different types of gasses and/or etching equipment. Generally speaking, there are three types of dry etching devices: (i) ion beam etching, (ii) ion-assisted etching (often termed reactive ion etching or "RIE"), and (iii) chemical etching or plasma etching. The first two etching techniques are often termed "directional" etching. That is, ion beams are directed at an angle preferably perpendicular to the upper surface of the wafer. Ion beam etching involves sputtering the upper wafer topological surface using a physical momentum transfer technique. While ion beam etching is substantially anisotropic, selectivity problems often arise. Plasma etching is more selective than ion beam etching, and is generally quite fast; however, plasma etching remains substantially isotropic, and is therefore less suitable for use in fabricating modern day VLSI devices. A few of the advantages of ion-assisted etching is that it is substantially anisotropic and is more selective than ion beam etching. Accordingly, ion-assisted etching or RIE etching remains a more optimal alternative, and one which is gaining momentum in modern day VLSI production.
Ion-assisted etching can be carried out using many types of commercial dry-etch systems. One of the more popular dry-etch systems, which achieves fine-line pattern transfer and profile retention, is one that is configured as a parallel-electrode reaction chamber. Power placed upon a pair of electrodes spaced from each other creates a potential difference within that space (or "gap") between the electrodes. The electric field potential causes the formation of ions sent from the plasma toward one of the electrodes. A silicon-based substrate with exposed thermal oxide placed within that gap thereby allows fine-line anisotropic etch of the oxide by the combination of a reactive chemical ambient as well as ions directed onto the oxide. End point detectors are integrated with the reactor to measure when the etch cycle is complete. End point detection employing laser interferometry, optical emission spectroscopy and mask spectroscopy are but a few well-known end point detection techniques.
While dry etching can be used to remove various types of thin films, such as silicon nitride, polysilicon, refractory metal, and organic films, it is the removal of oxides (SiO.sub.2) which forms the emphasis herein. Specifically, dry etch removal of thermally grown oxide, in a uniform fashion across contact areas is of prime importance in forming a highly conductive source/drain contact. Dry etch techniques which can uniformly remove thermally grown oxide in small areas such as contact areas would thereby constitute a substantial improvement over conventional oxide removal techniques.
Dry etch removal of a thermally grown oxide is dependent upon several process parameters. The effectiveness of etch removal is based not only upon the nature of the oxide being removed and the temperature of that oxide, but also upon the operating parameters of the dry etch reactor (i.e., the parallel electrode reactor). In the latter instance, careful control of the reactant gas flow, pumping pressure and excitation power as well as frequency of the reactor RF power must be maintained in order to optimally achieve uniform removal of small area thermal oxide films. If any of the aforesaid parameters are skewed from an optimal target setting, the result could be a less than desirable contact conductivity. For example, if the excitation power/frequency of the parallel electrodes is not optimally chosen, then removal of oxide within the contact regions could be far less than uniform. Further, not only must a proper mixture of gas species be chosen to remove oxide, but those gasses must be mixed and introduced into a properly pressurized chamber in order to ensure correct contact and intermingling across the wafer peaks and valleys (i.e., across the wafer topological elevation).
It is thereby desirable that the process parameters within a parallel electrode reactor be optimally chosen to remove thermally grown oxides in fine-line areas, such as source/drain areas. It is also desirable that thermal oxide be uniformly removed across the entire source/drain area as well as across the entire wafer. The thermal oxide must be removed at a uniform rate across certain polysilicon gate regions. Regardless of the underlying silicon-based material (either single crystal silicon or polycrystalline silicon) chosen, the processing parameters must be selected such that oxide is removed, either completely or partially above a silicon substrate or polysilicon gate without affecting the underlying silicon substrate or polysilicon. The parameters for dry etch removal of oxide must therefore be selected to cause minimal damage to the underlying film or substrate, and must be highly selective against etching the underlying material.